COURSE PROGRAMME



COURSE PROGRAMME



Online Short-Course on
“Advanced ADC Design Techniques”
By Prof. Seung-Tak Ryu (KAIST)

Dates: 5th/8th/12th/15th/26th/29th Sept. & 3rd/6th Oct. 2022

Live-Virtual Zoom Lectures


Online Short-Course on
“Advanced ADC Design Techniques”
By Prof. Seung-Tak Ryu (KAIST)

Dates: 5th/8th/12th/15th/26th/29th Sept. & 3rd/6th Oct. 2022

Live-Virtual Zoom Lectures


COURSE OUTLINE


This course addresses practical circuit design and layout techniques for successful implementation of advanced analog-to-digital converters (ADCs) with an in-depth discussion of circuit nonidealities.

The course begins by studying the essential building blocks for ADCs: sampling circuits and comparators. Various key concepts, including bandwidth, linearity, noise, top/bottom-plate sampling, boosting, offset reduction will be analyzed.

Then, we will focus on two representative Nyquist ADC architectures, Successive-Approximation Register (SAR) ADC and Pipelined ADC, starting from their fundamental concept to the state-of-the-art design and layout techniques.

More specifically, in SAR ADCs, we will discuss nonlinearity and switching energy of digital-to-analog converters (DACs), decision redundancies for error correction including integer-based non-binary SAR decision, architectural modifications for speed enhancement, and calibration techniques for performance robustness.

Time-interleaved (TI) ADCs and the channel mismatch issues will be also studied followed by mismatch calibration techniques.

In pipelined ADCs, we will address the residue inaccuracy issues and how various error sources in a residue amplifier (RA) or a multiplying-DAC (MDAC) affect the nonlinearity profile. Then, there will be a review of how pipelined ADCs have evolved, with a special focus on the RA design. Recent advanced design techniques, including pipelined-SAR ADCs and calibration schemes for residue inaccuracy compensation will be discussed.

The final lecture of the course is dedicated to practical tips for ADC circuit simulations and test measurements, including clock generation, power-supply separation, linearity measurement, FFT.

Each lecture includes design case studies and examples. There will also be a focus on design methodologies and good layout practice.

This course is intended primarily for analog designers with some experience in data converter design who do not have experience with advanced ADC design techniques. We will assume no familiarity with these advanced design techniques and introduce them throughout the course.


Duration: 16 hrs

Format: 8 ‘Live-Virtual’ Sessions, scheduled over a 4-week period, with twice-weekly, 2-hour lectures, including interactive Q&A and some hands-on work during the lectures. 

Work: Homework assignments (optional) will consolidate the learning from the lectures.

Included: Course notes (PDF), homework assignments (PDF), course home page, class forum, lecture playback (limited time) & attendance certificate.


Duration: 16 hrs

Format: 8 ‘Live-Virtual’ Sessions, scheduled over a 4-week period, with twice-weekly, 2-hour lectures, including interactive Q&A and some hands-on work during the lectures. 

Work: Homework assignments (optional) will consolidate the learning from the lectures.

Included: Course notes (PDF), homework assignments (PDF), course home page, class forum, lecture playback (limited time) & attendance certificate.


Online Short-Course on
“Advanced ADC Design Techniques”


Course Programme


All Lectures @ (13:00-15:00 UTC) = (14:00-16:00 WET) = (15:00-17:00 CET) = (09:00-11:00 ET) = (06:00-08:00 PT)


5th September 2022


Lecture #1 – ADC Essential Building Blocks: Sampling Circuit & Comparators
Switch Nonidealities, Clock-boosting Switches, Dynamic Comparators, Comparator Offset and Noise.


8th September 2022


Lecture #2 – SAR ADC: Fundamentals
Capacitive DAC Linearity and Switching Energy, Decision Redundancy, Nonbinary SAR ADC, Case Study.


12th September 2022


Lecture #3 – SAR ADC: Advanced Designs
Architectural Modifications (Subranging, Loop unrolled, Multi-bit/cycle, etc.), Calibration Techniques.


15th September 2022


Lecture #4 – SAR ADC: Time Interleaving
Sources of Channel Mismatch and Their Effect on Performance, Calibration Schemes, Case Study.


26th September 2022


Lecture #5 – Pipeline ADC: Fundamentals
Operational Principle, Residue Accuracy Requirements, Error Sources on Linearity Profile.


29th September 2022


Lecture #6 – Pipeline ADC: Residue Amp Design & Evolutions
Major Design Evolutions, Residue Amplifier Structures (Closed-loop, Open-loop), Case Study.


3rd October 2022


Lecture #7 – Pipeline ADC: Advanced Designs
Recent Residue Amps, Pipeline-SAR ADCs, Calibration Techniques, Case Study.


6th October 2022


Lecture #8 – Miscellaneous Techniques for ADC Design, Layout & Verification
Simulation Test-benches, CDAC Layout for High Linearity, Considerations for Measurement Setup.






Seung-Tak Ryu is a Professor at the School of Electrical Engineering at Korea Advanced Institute of Science and Technology (KAIST).

He received the B.S. degree in electrical engineering from Kyungpook National University, Korea, in 1997, and the M.S. and Ph.D. degrees from KAIST, Daejeon, Korea, in 1999 and 2004, respectively.

From 2001 to 2002, he was with the University of California at San Diego, La Jolla, CA, USA, as a Visiting Researcher, sponsored through the Brain Korea 21 (BK21) Program. In 2004, he joined Samsung Electronics, Yongin, South Korea, where he was involved in mixed-signal IP development.

From 2007 to 2009, he was with the Information and Communications University (ICU), Daejeon, as an Assistant Professor. He has been with the School of Electrical Engineering, KAIST, since 2009, where he is currently a Professor. His research interests include analog and mixed-signal integrated circuit (IC) design with an emphasis on data converters and sensors. He has in excess of 100 research publications (journal and conference) and more than 30 patents (international and domestic).

Dr. Ryu is a member of the Technical Program Committee (TPC) of Asian Solid-State Circuits Conference (ASSCC), Custom Integrated Circuits Conference (CICC), and European Solid-State Circuits Conference (ESSCIRC). He has served on the TPC of the IEEE International Solid- State Circuits Conference (ISSCC) and as a Guest Editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC), twice. He has been an Associate Editor of the IEEE SOLID-STATE CIRCUITS LETTERS (SSCL) since 2018. He is also serving as a Distinguished Lecturer for the IEEE Solid-State Circuits Society for the period of 2021-2022.


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