Dates: 4th/7th/11th/14th/18th/21st/25th/28th September 2023
Live-Virtual Zoom Lectures
Dates: 4th/7th/11th/14th/18th/21st/25th/28th September 2023
Live-Virtual Zoom Lectures
CMOS RF transceivers emerged as an academic research topic in the 1990s and swiftly made their way into consumer markets, driven by the rise of laptops and smartphones over the next three decades. As wireless technology evolves, new standards are constantly being introduced, necessitating improvements in power, performance, area, and cost (PPAC) in wireless devices to enhance our digital experiences.
This course provides a comprehensive overview of CMOS RF transceiver design, ranging from relevant signal processing concepts to real-world case studies. The course emphasizes the identification of design challenges and the discussion of circuit and system solutions when designing practical CMOS RF transceivers. Active participation from the course participants in the online sessions and offline course forums is highly encouraged.
This course begins by providing a review of basic signal processing concepts to establish foundational knowledge. We will then examine the evolution of CMOS RF transceiver architectures during the first decade of commercialization.
Moving forward, we will dive deeper into transceiver design, focusing on the unique differences and challenges specific to RF transceiver design compared to other analog-to-digital interface designs. Key specifications of both receivers and transmitters will be closely examined to provide a comprehensive understanding of their backgrounds.
Practical considerations within the context of mobile phones will be explored, covering topics that are directly relevant to product development and often go beyond what is typically covered in textbooks.
The course will also feature recent transceiver examples published in relevant literature as case studies. Through these real-life design examples, you will gain insights into the technical challenges faced by today’s RFIC designers and their approaches to overcoming them.
Lastly, we will conclude the course by discussing future challenges that may lie ahead for CMOS RF transceivers, to help you to anticipate and prepare for the evolving landscape in this field.
For each lecture, participants will receive optional homework assignments with mathematical/calculation questions and/or thought-provoking questions to encourage them to apply their understanding and experience, thereby further enhancing the learning beyond the lecture material.
This course is primarily intended for RF/Analog/Mixed-Signal IC design engineers seeking both a top-down view and practical knowledge of CMOS RF transceiver design for wireless applications. It is recommended to have some experience in RF/Analog IC design using CMOS process.
Duration: 16 hours
Format: 8 ‘Live-Virtual’ sessions, scheduled over a 4-week period, with twice-weekly, 2-hour lectures including open Q&A.
Work: Homework assignments (optional) will consolidate the learning from the lectures.
Included: Course notes (PDF), homework assignments (PDF), lecture recordings* (up to 12 months playback), class discussion forum (offline Q&A) and attendance certificate.
*Facilitates the opportunity to catch-up with missed lecture(s) due to time-zone difference, work deadlines, etc. or simply to review the lecture recording(s) at your own pace and convenience.
Fees:
Early-Bird Rate: EUR 495 (Payment/PO UNTIL 30th June 2023) Extended To 14th July 2023
Standard Rate: EUR 645 (Payment/PO FROM 3rd July 2023) From 17th July 2023
For course registration, more information or subscription to our newsletter
Duration: 16 hours
Format: 8 ‘Live-Virtual’ sessions, scheduled over a 4-week period, with twice-weekly, 2-hour lectures including open Q&A.
Work: Homework assignments (optional) will consolidate the learning from the lectures.
Included: Course notes (PDF), homework assignments (PDF), lecture recordings* (up to 12 months playback), class discussion forum (offline Q&A) and attendance certificate.
*Facilitates the opportunity to catch-up with missed lecture(s) due to time-zone difference, work deadlines, etc. or simply to review the lecture recording(s) at your own pace and convenience.
Fees:
Early-Bird Rate: EUR 495 (Payment/PO UNTIL 30th June 2023) Extended to 14th July 2023
Standard Rate: EUR 645 (Payment/PO FROM 3rd July 2023) From 17th July 2023
For registration, more information or subscription to our newsletter
4th September 2023
Lecture #1 – Sending Data Without Wire? Why CMOS For RF?
This lecture will cover relevant signal processing concepts. Then, we will explore the reasons behind the adoption of the not-so-RF-friendly CMOS process for RF transceivers.
Keywords: Frequency Translation, Time/Frequency Domain Signal Representation, CMOS, PPAC, etc.
7th September 2023
Lecture #2 – Why So Many Architectures?
Following up from Lecture #1, we will examine the evolution of various transceiver architectures throughout time and discuss pros and cons.
Keywords: Wireless Applications, Super-Heterodyne, Low-IF, Zero-IF, Wireless Applications, etc.
11th September 2023
Lecture #3 – Why So Much to Know for RF Transceivers?
This lecture will discuss key specifications for the receiver and transmitter and explore their relationship to system performance. We will also cover some building block circuits.
Keywords: Noise, Intermodulation, EVM, Interference, LNA, Mixer, Filter, Data-Converters, etc.
14th September 2023
Lecture #4 – Any Practical Considerations?
From IC layout to PCB design, designing and integrating RFICs into the overall system require careful attention in every step. We will discuss some practical considerations to keep in mind when designing RFICs for mobile phones.
Keywords: Floorplan, On-Chip/PCB Coupling, RFIC-Modem Interface, Power-Management, etc.
18th September 2023
Lecture #5 – Can We Do Better?
Advanced mixed-signal techniques push the circuit performance beyond what could be achieved by analog techniques alone. But at the same time, they introduce complexity. In this lecture, we will examine the trade-offs involved.
Keywords: Open-Loop For RF, Calibration, Duty-Cycling, Power-Saving, ET/APT, etc.
21st September 2023
Lecture #6 – Case Study #1: Multi-band Receiver
Case studies are important to bridge the gap between paper design concepts to silicon results. The first case study here is about multi-band receivers for LTE applications.
Keywords: Receiver, Multi-Band, LTE, Carrier-Aggregation, Inter/Intra-Band, LNA, etc.
25th September 2023
Lecture #7 – Case Study #2: IoT SoC
For IoT, cost is crucial, and we will examine how reconfigurable circuit design and RF-digital SoC implementation helped achieving the goal.
Keywords: NB-IoT, GNSS, SoC, Reconfigurable Circuit, etc.
28th September 2023
Lecture #8 – Case Study #3: FR2 Chipset & Future Challenges
FR2 is a mm-Wave frequency band for 5G, and we will study a chip-set example, its unique challenges, and solutions for mobile applications. We will also discuss challenges for future wireless devices.
Keywords: 5G, FR2, Chipset, Phase-Array, Mobile Form Factor, Process Technology For RF, etc.
Thomas Byunghak Cho is currently an Invited Professor at the School of Electrical Engineering at the Korea Advanced Institute of Science and Technology (KAIST) in S. Korea. He received his B.S. degree from UCLA, USA in 1989, and his M.S. and Ph.D. degrees from UC Berkeley, USA in 1991 and 1995, respectively.
In 1996, he started his professional career at Level One Communications in San Francisco, USA. He was one of the lead IC designers in developing CMOS RF transceiver products, which were among the earliest in the industry at that time. In 2000, he co-founded Wireless Interface Technologies in Dublin, USA, with a focus on developing CMOS RF transceiver products for WLAN and Bluetooth applications.
From 2004 to 2011, he worked at Marvell Semiconductor in Santa Clara, USA, concentrating on CMOS RF/analog IC product development for a wide range of wireless and wireline connectivity applications. In 2012, he joined Samsung Electronics in Hwaseong-si, South Korea, where he held executive positions and led multiple engineering teams. His responsibilities included the development of cellular/connectivity RF transceivers, analog/mixed-signal IPs, and multimedia IPs. Additionally, he was responsible for managing digital physical implementation and design verification activities.
Since 2022, he has been serving as an Invited Professor at KAIST while also providing technical advisory services to IC design companies. His technical interests include RF/analog/mixed-signal circuit designs for wireless and wireline communication systems, low-power digital circuit techniques for processors, and analog-to-digital interface circuit designs for sensor applications.
He is a co-recipient of the Jack-Kilby Award for Outstanding Student Paper at ISSCC 1998 and, in 2021, his RFIC team at Samsung received the President’s Award at the 22nd Broadcasting Technology Awards by the Ministry of Science and ICT in S. Korea. He has authored or co-authored over 40 journal articles and conference papers and holds more than 40 patents. He is an IEEE Fellow.