COURSE OUTLINE

Progress in computation and communication is increasingly bottlenecked by integrated circuit I/O. The circuits that communicate data between chips have gone from simple buffers to modern full-fledged digital modems. As such, they require a system-level approach and understanding.

The bandwidth limitations of electrical interconnect demand sophisticated signal processing to ensure signal integrity. Equalization and maximum likelihood sequence detection combine broadband analog/mixed-signal design and high-performance DSP to combat these bandwidth limitations.

Meanwhile, timing margins of a fraction of a picosecond demand precise clocking. Again, mixed-analog/mixed-signal and DSP are combined to meet the challenges. Interactions between the analog front-end, equalization, timing recovery, and forward error correction are critical.

In spite of all this sophistication, electrical links are simply impractical in some applications, and optical links are being increasingly used and must therefore be understood by modern practitioners. This may include so-called “pluggable” optical modules, or miniaturized optical “engines” placed on a circuit board or even within an IC package.

This course conveys a system-level perspective that will allow circuit designers to appreciate all critical aspects of wireline transceivers: from physical channel impairments, all the way through the algorithms required for robust links. By the end of the course, attendees will be armed to combat tomorrow’s transceiver challenges at 200 Gbps and above.

Exciting Python-based homework assignments (optional) will consolidate knowledge gained from our lectures, e.g. 2-PAM & 4-PAM waveforms with filtering, coding & decoding with burst of errors, channel modeling with non-idealities, CTLE circuit with poles & zeros, equalization & trellis, Rx & Tx clock jitter, optical modulator & RLM, etc.

The target audience for this course are those looking to get into wireline transceivers as well as those already working on wireline transceivers. The participants will learn all the main building blocks of a wireline transceiver system and the interaction between them, as well as the requirements of various sub-systems, depending on the application. The course content gives more emphasis to system-level understanding of wireline transceivers. Some of the lectures will also review schematic diagrams of key transceiver blocks.