COURSE PROGRAMME



COURSE PROGRAMME



Online Short-Course on

“Modern Wireline Transceivers –
The Backbone of The Digital Age”

By Prof. Tony Chan Carusone (University of Toronto)

Dates: 9th/12th/16th/19th/23rd/26th/30th/2nd Jan./Feb. 2023

Live-Virtual Zoom Lectures


Online Short-Course on

“Modern Wireline Transceivers –
The Backbone of The Digital Age”

By Prof. Tony Chan Carusone (University of Toronto)

Dates: 9th/12th/16th/19th/23rd/26th/30th/2nd Jan./Feb. 2023

Live-Virtual Zoom Lectures


COURSE OUTLINE


Progress in computation and communication is increasingly bottlenecked by integrated circuit I/O. The circuits that communicate data between chips have gone from simple buffers to modern full-fledged digital modems. As such, they require a system-level approach and understanding.

The bandwidth limitations of electrical interconnect demand sophisticated signal processing to ensure signal integrity. Equalization and maximum likelihood sequence detection combine broadband analog/mixed-signal design and high-performance DSP to combat these bandwidth limitations.

Meanwhile, timing margins of a fraction of a picosecond demand precise clocking. Again, mixed-analog/mixed-signal and DSP are combined to meet the challenges. Interactions between the analog front-end, equalization, timing recovery, and forward error correction are critical.

In spite of all this sophistication, electrical links are simply impractical in some applications, and optical links are being increasingly used and must therefore be understood by modern practitioners. This may include so-called “pluggable” optical modules, or miniaturized optical “engines” placed on a circuit board or even within an IC package.

This course conveys a system-level perspective that will allow circuit designers to appreciate all critical aspects of wireline transceivers: from physical channel impairments, all the way through the algorithms required for robust links. By the end of the course, attendees will be armed to combat tomorrow’s transceiver challenges at 200 Gbps and above.

The target audience for this course are those looking to get into wireline transceivers as well as those already working on wireline transceivers. The participants will learn all the main building blocks of a wireline transceiver system and the interaction between them, as well as the requirements of various sub-systems, depending on the application. The course content gives more emphasis to system-level understanding of wireline transceivers. Some of the lectures will also review schematic diagrams of key transceiver blocks.


Duration: 16 hrs

Format: 8 ‘Live-Virtual’ Sessions, scheduled over a 4-week period, with twice-weekly, 2-hour lectures including interactive Q&A. 

Work: Homework assignments (optional) will consolidate the learning from the lectures.

Included: Course notes (PDF), homework assignments (PDF), course home page, class forum, lecture playback (limited time) & attendance certificate.


Duration: 16 hrs

Format: 8 ‘Live-Virtual’ Sessions, scheduled over a 4-week period, with twice-weekly, 2-hour lectures including interactive Q&A. 

Work: Homework assignments (optional) will consolidate the learning from the lectures.

Included: Course notes (PDF), homework assignments (PDF), course home page, class forum, lecture playback (limited time) & attendance certificate.


Course Programme


All Lectures @ (14:00-16:00 UTC) = (15:00-17:00 WET) = (16:00-18:00 CET) = (10:00-12:00 ET) = (07:00-09:00 PT)


9th January 2023


Lecture #1 – Trends and Applications
The need for SerDes; Evolution of SerDes; Standards: Ethernet, OIF-CEI; Die-to-Die applications; Optical applications.


12th January 2023


Lecture #2 – Modulation and Coding
NRZ vs. PAM; Forward looking: Discrete-Multitone; Introduction to Forward Error Correction.


16th January 2023


Lecture #3 – Channel Modeling
Skin effect and dielectric loss; Frequency-domain and time-domain modeling; Open-source python library for channel modelling.


19th January 2023


Lecture #4 – Equalization
Analog equalization; Digital equalization: FFE, DFE.


23rd January 2023


Lecture #5 – Maximum Likelihood Sequence Detection
Explanation; Implementation.


26th January 2023


Lecture #6 – Clocking
Clocking architectures and specifications; Timing recovery; Clocking building blocks.


30th January 2023


Lecture #7 – Introduction to Optical Communication
Optoelectronic components: optical fibre, connectors, lasers, modulators, photodiodes; Unique optical link specifications; Unique aspects of optical SerDes design.


2nd February 2023


Lecture #8 – Case Studies






Tony Chan Carusone has been a faculty member at the University of Toronto since completing his Ph.D. there in 2002. He has co-authored eight award-winning papers on chip-to-chip and optical communication circuits, ADCs, and clock generation. He has also been a consultant to industry since 1997. He is currently the Chief Technology Officer of Alphawave IP in Toronto, Canada.

Dr. Chan Carusone was a Distinguished Lecturer for the IEEE Solid-State Circuits Society 2015-2017 and served on the Technical Program Committee of the International Solid-State Circuits Conference from 2015-2021. He co-authored the latest editions of the classic textbooks “Analog Integrated Circuit Design” along with D. Johns and K. Martin, and “Microelectronic Circuits” along with A. Sedra and K.C. Smith. He has served as Editor-in-Chief of the IEEE Transactions on Circuits and Systems II: Express Briefs, an Associate Editor for the IEEE Journal of Solid-State Circuits, and is now Editor-in-Chief of the IEEE Solid-State Circuits Letters. He is a Fellow of the IEEE.


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