COURSE OUTLINE

The ever-increasing appetite for higher data-rates, from communication to automotive to industrial to healthcare to cloud computing and AI, is the driving force behind the continued research and development of multi-GSPS SAR-type ADCs at extended resolutions.

This cutting-edge course celebrates twenty years of remarkable Time-Interleaved (TI) SAR ADC architecture innovations and inspired circuit design techniques, since the first ever reported 6-bit 600MSPS TI SAR ADC implementation on 90nm Digital CMOS at ISSCC 2004, by providing an in-depth walkthrough from theoretical to practical considerations on extreme speed SAR ADCs. The participants will be guided from fundamental concepts to state-of-the-art implementations followed by practical case studies, continuously exploring new frontiers to extend present day performance.

The course begins by taking a deep dive into interleaver topologies of massive TI SAR ADCs, discussing non-idealities, design considerations, modeling techniques and detailed case study.

This is followed by paying specific attention to the design challenges and solutions of peripheral blocks that are essential for high-performance massive TI ADCs: the input buffer and reference buffer.

Other key SAR ADC blocks, i.e. extreme sampler, comparator, residue amplifier and clocking, are also examined, progressing from fundamental concepts to advanced techniques followed by comprehensive case studies.

Subsequently, the course explores two architectures renowned for their high-speed and energy-efficiency: SAR and Pipeline-SAR ADCs. The emphasis will be on their high-speed implementation varieties, which are specifically fit for extensive interleaving. Once again, the lectures follow a progression from fundamental concepts to state-of-the-art advancements, summarizing with case studies.

Moving forward, digitally-assisted TI SAR ADCs are presented with an in-depth discussion of inter-channel non-idealities and calibration techniques, including input buffer distortion calibration.

The course will conclude with a discussion of good layout practices, tips and considerations for successful implementation of advanced, extremely high-speed SAR-type ADCs.

The recommended target audience for this course are analog and mixed-signal design engineers looking to get into ADC design as well as those already working with ADCs, interested to learn advanced state-of-the-art ultra-high-speed ADC design techniques. Familiarity with fundamental ADC concepts will be beneficial but is not a pre-requisite.