Sample Lecture – “Nanoscale Analog CMOS Design” Online Course (2021)
Sample Homework #1A – “Nanoscale Analog CMOS Design” Online Course (2021)
Sample Homework #1B – “Nanoscale Analog CMOS Design” Online Course (2021)
Sample Homework #3 – “Nanoscale Analog CMOS Design” Online Course (2021)
The course addresses the design of high-performance analog circuits in nanoscale CMOS technologies that offer analog circuit designers both benefits and challenges.
With transistor performance increasing and their size decreasing, parasitics are increasingly predominant contributors to overall circuit performance. Low supply voltages favour simple analog subcircuits and make power supply integrity critical for first-time-right-silicon.
The course begins by reviewing the transistor short-channel-length characteristics that particularly impact analog design in nanoscale technologies. We then discuss basic analog amplifier circuits compatible with low supply voltages and nanoscale CMOS technologies.
Subsequent lectures cover references and regulators, clock distribution and dynamic analog circuits. The final two lectures consider the design of ADCs and common pitfalls when integrating complex analog IP in nanoscale technologies.
Each lecture includes analog design case studies in technologies including 28nm bulk CMOS, 28nm FD-SOI, and 16nm FinFET. There will also be a focus on step-by-step methodologies for high-quality power supply integrity, low-jitter clock distribution, good layout practice, etc.
The course is intended primarily for analog designers with some experience in traditional bulk-CMOS technologies who may or may not have experience with technologies below 30nm. We will assume no familiarity with these advanced technologies and introduce them in the first two lectures.
Lecture #1 – CMOS Device Scaling & Modeling
Device scaling, short-channel length effects, analog design on bulk CMOS technologies below 30nm.
Lecture #2 – Advanced CMOS Technologies: SOI & FinFET
Impact on transistor model parameters, analog FOM & layout strategies. Reliability effects.
Lecture #3 – Amplifier Design in Nanoscale CMOS
Design of current mirrors & amplifier circuits. Suitable OTA topologies for low supply-voltage.
Lecture #4 – References, Regulators & Power Integrity
Differential reference circuits & voltage regulation. Power distribution in ICs. Power integrity analysis.
Lecture #5 – Nanoscale CMOS Clocking
Jitter sources, amplification & power-supply-induced jitter. CMOS buffering & clock distribution.
Lecture #6 – Dynamic Comparators & Amplifiers
Applications of dynamic amplifiers (as integrators) in high-speed receivers. Dynamic comparators.
Lecture #7 – ADC-Based Receivers in Nanoscale CMOS
High-speed ADCs: folding-flash, binary search & CT pipelined. Combatting mismatch & applications.
Lecture #8 – Real-Life Cautionary Tales
Common design & layout errors, integrating large designs, power & clock routing, non-working chips.
Duration: 16 hours
Format: 8 x 2-hour recorded lectures including interactive Q&A.
Work: Homework assignments (optional) will consolidate the learning from the lectures.
Included:
- Course notes (PDF)
- Homework assignments (PDF)
- Lecture recordings (8 weeks playback access)
- Course homepage
- Class discussion forum (offline Q&A)
- Recommended reading list
- Extra material
Tony Chan Carusone (S’96–M’02–SM’08) received his Ph.D. from the University of Toronto in 2002 and has since been a professor with the Department of Electrical and Computer Engineering at the University of Toronto. He is also an occasional consultant to industry in the areas of integrated circuit design and digital communication.
Prof. Chan Carusone co-authored the Best Student Papers at the 2007, 2008 and 2011 Custom Integrated Circuits Conferences, the Best Invited Paper at the 2010 Custom Integrated Circuits Conference, the Best Paper at the 2005 Compound Semiconductor Integrated Circuits Symposium, and the Best Young Scientist Paper at the 2014 European Solid-State Circuits Conference. He co-authored the popular textbooks “Analog Integrated Circuit Design” (along with D. Johns and K. Martin) and “Microelectronic Circuits,” 8th edition (along with A. Sedra, K.C. Smith and V. Gaudet). He was Editor-in-Chief of the IEEE Transactions on Circuits and Systems II: Express Briefs in 2009, an Associate Editor for the IEEE Journal of Solid-State Circuits 2010-2017 and is now Editor-in-Chief of the IEEE Solid-State Circuits Letters. He was a Distinguished Lecturer for the IEEE Solid-State Circuits Society 2015-2017 and currently serves on the Technical Program Committee of the International Solid-State Circuits Conference.
