Sample Lecture – “Advanced ADC Design Techniques” Online Course (2022)
Sample Homework #1 – “Advanced ADC Design Techniques” Online Course (2022)
Sample Homework #2 – “Advanced ADC Design Techniques” Online Course (2022)
This course addresses practical circuit design and layout techniques for successful implementation of advanced analog-to-digital converters (ADCs) with an in-depth discussion of circuit nonidealities.
The course begins by studying the essential building blocks for ADCs: sampling circuits and comparators. Various key concepts, including bandwidth, linearity, noise, top/bottom-plate sampling, boosting, offset reduction will be analyzed.
Then, we will focus on two representative Nyquist ADC architectures, Successive-Approximation Register (SAR) ADC and Pipelined ADC, starting from their fundamental concept to the state-of-the-art design and layout techniques.
More specifically, in SAR ADCs, we will discuss nonlinearity and switching energy of digital-to-analog converters (DACs), decision redundancies for error correction including integer-based non-binary SAR decision, architectural modifications for speed enhancement, and calibration techniques for performance robustness.
Time-interleaved (TI) ADCs and the channel mismatch issues will be also studied followed by mismatch calibration techniques.
In pipelined ADCs, we will address the residue inaccuracy issues and how various error sources in a residue amplifier (RA) or a multiplying-DAC (MDAC) affect the nonlinearity profile. Then, there will be a review of how pipelined ADCs have evolved, with a special focus on the RA design. Recent advanced design techniques, including pipelined-SAR ADCs and calibration schemes for residue inaccuracy compensation will be discussed.
The final lecture of the course is dedicated to practical tips for ADC circuit simulations and test measurements, including clock generation, power-supply separation, linearity measurement, FFT.
Each lecture includes design case studies and examples. There will also be a focus on design methodologies and good layout practice.
This course is intended primarily for analog designers with some experience in data converter design who do not have experience with advanced ADC design techniques. We will assume no familiarity with these advanced design techniques and introduce them throughout the course.
Lecture #1 – ADC Essential Building Blocks: Sampling Circuit & Comparators
Switch Nonidealities, Clock-boosting Switches, Dynamic Comparators, Comparator Offset and Noise.
Lecture #2 – SAR ADC: Fundamentals
Capacitive DAC Linearity and Switching Energy, Decision Redundancy, Nonbinary SAR ADC, Case Study.
Lecture #3 – SAR ADC: Advanced Designs
Architectural Modifications (Subranging, Loop unrolled, Multi-bit/cycle, etc.), Calibration Techniques.
Lecture #4 – SAR ADC: Time Interleaving
Sources of Channel Mismatch and Their Effect on Performance, Calibration Schemes, Case Study.
Lecture #5 – Pipeline ADC: Fundamentals
Operational Principle, Residue Accuracy Requirements, Error Sources on Linearity Profile.
Lecture #6 – Pipeline ADC: Residue Amp Design & Evolutions
Major Design Evolutions, Residue Amplifier Structures (Closed-loop, Open-loop), Case Study.
Lecture #7 – Pipeline ADC: Advanced Designs
Recent Residue Amps, Pipeline-SAR ADCs, Calibration Techniques, Case Study.
Lecture #8 – Miscellaneous Techniques for ADC Design, Layout & Verification
Simulation Test-benches, CDAC Layout for High Linearity, Considerations for Measurement Setup.
Duration: 16 hours
Format: 8 x 2-hour recorded lectures including interactive Q&A.
Work: Homework assignments (optional) will consolidate the learning from the lectures.
Included:
- Course notes (PDF)
- Homework assignments (PDF)
- Lecture recordings (8 weeks playback access)
- Course homepage
- Class discussion forum (offline Q&A)
- Recommended reading list
- Extra material
Seung-Tak Ryu received the M.S. and Ph.D. degrees in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 1999 and 2004, respectively.
From 2001 to 2002, he was with the University of California, San Diego, CA, USA, as a Visiting Researcher. He began his professional career in 2004 with Samsung Electronics, Yongin, South Korea, where he worked on the development of mixed-signal IPs. From 2007 to 2009, he was an Assistant Professor with the Information and Communications University (ICU), Daejeon.
Since 2009, he has been a Faculty Member with the School of Electrical Engineering, KAIST, where he is currently a Professor. His research interests include analog and mixed-signal integrated circuit (IC) design, particularly in the areas of data converters and sensors.
Dr. Ryu is actively involved in the technical community. He is a member of the Technical Program Committees (TPC) for the IEEE International Solid-State Circuits Conference (ISSCC), the Asian Solid-State Circuits Conference (ASSCC), and European Solid-State Circuits Conference (ESSCIRC). He previously served on the TPC of the IEEE Custom Integrated Circuits Conference (CICC) as Chair of the Data Converter Subcommittee. He has twice served as a Guest Editor for the IEEE Journal of Solid-State Circuits (JSSC) and was an Associate Editor for the IEEE Solid-State Circuits Letters (SSCL) from 2018 to 2023. From 2021 to 2022, he served as a Distinguished Lecturer for the IEEE Solid-State Circuits Society. He currently serves as an Associate Editor for both the IEEE Open Journal of Circuits and Systems (OJ-CAS) and the IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS).
