“High-Performance SERDES Design” – Prof. Sam Palermo (Texas A&M University)

Current high-performance serializer/deserializer (SERDES) transceivers are operating in excess of 200Gb/s to support growing I/O bandwidth demands. This course covers key system-level topics and in-depth circuit design techniques for successful implementation of these advanced SERDES transceivers.

The course begins with a brief overview of key channel characteristics, modulation techniques, and link analysis approaches. We will also walk through a recent >200Gb/s transceiver to motivate the remainder of the course circuit design topics.

Then, we will focus on transmitter output drivers and receiver front-end circuits. Various key concepts, including swing enhancement techniques, impedance control, bandwidth extension, high-bandwidth analog front-ends, and high-performance comparators, will be analyzed.

Equalizers are required to compensate for frequency-dependent channel loss. We will discuss transmit-side feed-forward equalizers (FFEs), implemented in the analog domain or with digital-to-analog converter (DAC)-based transmitters, and receive-side FFE, continuous-time linear equalizers (CTLEs), and decision-feedback equalizers (DFEs). Digital signal processor (DSP)-based equalization, enabled by high-speed analog-to-digital converter (ADC)-based receivers, will also be covered, along with applicable high-speed ADC topologies.

These high-performance transceivers require sub-ps noise clocks with precise timing alignment. High-performance clock generation, distribution, and recovery circuits will be detailed.

Finally, longer-reach signaling is possible with optical transceivers that have traditionally been pluggable modules, but are now migrating inside the package to more efficiently meet interconnect bandwidth requirements. We will cover key photonic devices, transmit drivers, and receiver front-ends for these optical transceivers.

For each lecture, participants will receive optional homework assignments that involve modeling key concepts to further enhance the learning beyond the lecture material.

This course is primarily intended for Analog/Mixed-Signal IC design engineers and research graduates, with some exposure to SERDES transceivers, that are interested in learning advanced design techniques for recent state-of-the-art transceivers. We will assume no familiarity with these advanced design techniques and introduce them throughout the course. Extensive transistor-level schematics of key transceiver blocks will be covered throughout the course.