“Precision Low-Dropout Regulators” – Prof. Yan Lu (Tsinghua University)

Noise-sensitive analog front-ends in System-on-Chip (SoC) and mixed-signal designs rely on Low-Dropout Regulators (LDOs) to deliver high power supply rejection (PSR) and fast transient response which are critical for maintaining on-chip power integrity. As essential building blocks in modern SoCs, LDOs must balance several trade-offs: power efficiency versus speed, dropout voltage versus PSR, and precision versus quiescent current and loop bandwidth. The move toward capacitor-less designs, which frees valuable I/O pins, introduces further design challenges, particularly in achieving high PSR and minimizing transient voltage undershoot.

This short-course covers the fundamental principles of LDO design, practical implementation techniques, and in-depth control loop analysis. It explores fully integrated, capacitor-less LDO topologies, offering real-world case studies of analog, digital, and distributed LDO architectures suited for large-scale SoC applications in nanoscale CMOS technologies.

The course begins with an intuitive introduction to key design concepts, including power transistor selection, gate-drive buffer design, dynamic biasing techniques, and PSR design considerations. Existing LDO architectures are reviewed through the framework of classical PID control theory, offering a simplified approach to understanding complex multi-loop designs.

Next, we’ll examine practical techniques and LDO design variants. Topics include feedforward ripple cancellation, LDOs with cascode power transistors, digitally controlled and synthesizable LDOs, and distributed LDO architectures designed for robust operation in large-scale systems.

In the final section, two detailed design and simulation projects are presented, one focused on achieving high bandwidth and the other on maximizing PSR. The participants will have the opportunity to develop and compare their own design solutions based on project parameters.

Each lecture is complemented by optional homework assignments that encourage participants to apply and extend their learning beyond the classroom. These exercises may involve SPICE simulations or analytical circuit design problems, offering practical experience that reinforces key concepts.

This course is aimed at analog, power management, and mixed-signal IC design engineers who wish to acquire practical knowledge of high-performance LDO circuits and a top-down understanding of advanced LDO topologies. The participants will explore a range of fully integrated LDOs, including analog, digital, and distributed architectures. Familiarity with fundamental LDO concepts will be beneficial.