“Multi-GSPS Nyquist DACs” – Dr. Gabriele Manganaro (MediaTek)

Original price was: €745.00.Current price is: €495.00.

Driven by the demand for higher data rates in multi-gigabit communications, medical imaging, instrumentation and defence systems, multi-GSPS Nyquist data converters are critical enablers of modern signal synthesis. This course provides a comprehensive, deployment-focused guide to high-performance Digital-to-Analog Converters (DACs), bridging the divide between theoretical architecture and silicon reality. The curriculum focuses primarily on dominant high-speed current-steering designs and emerging switched-capacitor topologies, guiding participants from first principles to state-of-the-art implementations. Through an intuitive, interactive approach, attendees will master impairment analysis to evaluate how static and dynamic non-idealities impact signal purity. Special emphasis is placed on advanced mitigation techniques, circuit calibration methods, and robust layout and floorplanning strategies required to overcome silicon parasitics. Backed by practical case studies, targeted homework, and two dedicated real-world design project sessions (14-bit, 1GSPS DAC and 7-bit, 28GSPS TI Self-Cal DAC) utilizing Spectre simulations, this course equips both emerging and seasoned engineers with the exact toolset needed to design functional, high-performance DACs.

Early-Bird Rate: €495 (Until 26th June 2026)
Standard Rate: €745 (From 29th June 2026)

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“Multi-GSPS Nyquist DACs” Online Course (2026)

Course Outline

Digital-to-Analog Converters (DACs) serve as the backbone of modern signal synthesis, bridging the digital and physical worlds. They are the critical enablers for a vast array of applications, ranging from multi-gigabit wireless and wired communications to precision instrumentation, medical imaging, and next-generation defence systems.

This course provides a comprehensive guide to the dominant architectures, with a primary focus on high-speed current-steering designs and emerging switched-capacitor DACs. Through an intuitive, interactive approach, the curriculum synthesizes theoretical concepts and state-of-the-art implementation, guiding participants from first principles to modern design techniques.

Core content includes:

Architectural Fundamentals: Examine foundational principles and basic circuit implementations of high-speed DACs.

Impairment Analysis: Identify key performance impairments and evaluate their impact on output signal purity.

Advanced Mitigation Techniques: Implement circuit calibration techniques and layout strategies used to overcome non-idealities and push performance limits.

Design Trade-offs: Analyse cutting-edge silicon-proven examples to understand the critical trade-offs between speed, power, and linearity.

This course integrates interactive lectures with rigorous practical application. Participants will develop both an intuitive and quantitative understanding of how underlying circuit behaviours translate to DAC performance in both the time and frequency domains. Detailed case studies, industry-standard layout/floorplanning strategies, and advanced simulation methodologies reconcile system-level architecture with silicon-level reality.

To solidify learning, the course features targeted homework assignments designed to bridge the divide between theoretical derivation and practical design. These optional assignments include Spectre simulations and behavioural modeling to characterise circuit dynamics against design calculations.

Two dedicated sessions are reserved for high-impact, real-world design projects tailored to the stringent requirements of wireless and high-speed wired communication. These projects will empower designers to apply the concepts covered in the regular lectures into functional designs. These sessions are augmented with practical simulation techniques, best-in-class design practices, and an analysis of common design pitfalls to avoid in silicon.

A working knowledge of analog IC design is required for this course. While the curriculum offers seasoned engineers a chance to reinforce their mastery and provides system architects with a deep dive into practical implementation, it is perfectly tailored for emerging engineers and research students seeking to launch a specialised career in high-performance data conversion.

Lecture List

All Lectures @ (23:00-01:00 Tokyo) = (16:00-18:00 Milan) = (15:00-17:00 Dublin) = (10:00-12:00 Boston) = (07:00-09:00 San Diego)

7th September 2026
Lecture #1 – DAC Fundamentals
Synthesis using Currents/Resistors/Capacitors; Architectures/Segmentation; DC Transfer Characteristic and Metrics.

10th September 2026
Lecture #2 – Mismatch and Static Calibration
Mismatches; Static Non-Idealities; Bias and Supply I*R Drops; Current Calibration; Layout Techniques.

14th September 2026
Lecture #3 – Dynamic Operation and Performance
Dynamic Performance Metrics; NRZ and RTZ; Interpolation; Dynamic Element Matching.

17th September 2026
Lecture #4 – Analog Techniques for Improved Dynamic Performance
Dynamic Non-Idealities; Code Dependence vs Constant Activity; Differential Quad Switching; Layout and Floorplans.

21st September 2026
Lecture #5 – Design Project #1: 14-bit, 1GSPS DAC
Wireless Communication Case Study; From-Specs-to-Sims; Step-by-Step Design and Practical Simulation Techniques; Abstraction Levels and Macros; Special fout/fs Ratios; Trading Accuracy with Run Time. Layout Techniques; Best Practices and Common Mistakes.

24th September 2026
Lecture #6 – Advanced Calibration and Error Cancellation
Pre-/Post-Distortion Cancellation; Pulsed Error Pre-Distortion; Mismatch Noise Cancellation; ISI Cancellation.

28th September 2026
Lecture #7 – Time-Interleaving
Dynamic Amplifiers

1st October 2026
Lecture #8 – Design Project #2: 7-bit, 28GSPS Time-Interleaved and Self-Calibrated DAC
Wired Communication Case Study; Integrating Knowledge from Design Project #1 and Subsequent Lectures; Ultra-High-Speed DAC Design and Simulation; Time-Interleaving; Timing Control; Floorplanning and Layout.

Features & Format

Duration: 16 hours

Format: 8 x 2-hour ‘Live-Virtual’ lectures (including Q&A), spread over 4-weeks. Attendance to the live lecture(s) is encouraged but not compulsory*.

Work: Homework assignments (optional) will consolidate the learning from the lectures.

Included: 

  • Course notes (PDF)
  • Homework assignments (PDF)
  • Lecture recordings* (up to 12 months playback access)
  • Course homepage
  • Class discussion forum (offline Q&A)
  • Recommended reading list
  • Extra material
  • Attendance certificate

* Up to 12 months of on-demand access facilitates participants to revisit recorded sessions anytime or catch up at their own pace.

About The Presenter

Gabriele Manganaro received the Dr. Eng. and Ph.D. degrees in electronics from the University of Catania, Italy, in 1994 and 1997, respectively.

He worked at Texas Instruments, Engim, National Semiconductor and Analog Devices. He joined MediaTek, Woburn, MA, USA, in 2021, as a Director of Technology.

He coauthored more than 70 peer-reviewed papers and three books, notably Advanced Data Converters (Cambridge University Press, 2011), and has been granted 20 U.S. patents.

He was a recipient of scientific awards, including the 1995 CEU Award from the Rutherford Appleton Laboratory, U.K., the 1999 IEEE Circuits and Systems Outstanding Young Author Award, and the 2007 IEEE European Solid-State Circuits Conference Best Paper Award.

Dr. Manganaro was elevated to IEEE Fellow in 2016 and IET Fellow in 2009 and is a member of the Sigma Xi scientific honor society. He currently serves as the Vice-President for Publications for the IEEE Circuits and Systems Society (CASS) for 2023–2026 and is a Distinguished Lecturer for the IEEE Solid-State Circuits Society (2019–2020, 2026–2027). His editorial service includes roles as Editor-in-Chief (2012–2013) for the IEEE Transactions on Circuits and Systems I: Regular Papers, following tenures as Associate and Deputy Editor-in-Chief. He was also the inaugural Editor-in-Chief for the IEEE Open Journal of Circuits and Systems (2020–2022). Additionally, he served on the ISSCC Data Converters Technical Sub-Committee (2005–2012), the IEEE CASS Board of Governors (2016–2018), and has been an Industry Advisory Member for the Proceedings of the IEEE (2019–2024), as well as a member of multiple technical committees for the Semiconductor Research Corporation since 2019.

Publications

DAC Patents (Selected)

[2017] Randomized quad switching
[2015] Complementary switches in current switching digital to analog converters
[2008] Method and apparatus to balance reference settling in switched-capacitor pipelined digital to analog converter
[2008] Parallel Digital-to-Analog Converter
[2007] Transresistance amplifier
[2007] Analog Calibration of a current source array at low supply voltage
[2006] Current steering digital to analog converter with improved dynamic linearity
[2006] Calibration of a current source array
[2004] High linearity digital to analog converter

DAC Publications (Selected)

[2013] Advances in Analog and RF IC Design for Wireless Communication Systems
[2012] Advanced Data Converters

[2026] Calibration for High-Speed, High-Resolution DACs
[2023] A 14b 16GS/s Time-Interleaving Direct-RF Synthesis DAC with T-DEM Achieving -70dBc IM3 up to 7.8GHz in 7nm
[2022] An Introduction to High Data Rate Current-Steering Nyquist DACs: Fasten your belts
[2022] Ultra-High-Data-Rate ADCs and DACs: Architectures and Implementations
[2004] A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizer

Course Report