“Ultra-Short-Reach Die-to-Die Link Design” – Prof. Sudip Shekhar (UBC)

Chiplets, advanced packaging, and high-bandwidth memory (HBM) are driving ultra-short-reach (USR) and die-to-die (D2D) links that span millimetres or centimetres yet deliver multiple terabits per second of aggregate bandwidth. Energy efficiency, bandwidth density, latency, signal integrity, and circuit area are therefore critical alongside per-lane data rate.

These links favour wide parallel interfaces, single-ended or ground-referenced signalling, modest channel loss, and forwarded-clock timing rather than the complex equalization and clock-recovery used in long-reach links. Their design requires understanding TX/RX circuits, package channels, timing, and advanced packaging. The course develops these concepts from first principles through practical circuit design and simulation.

USR system architectures, D2D interconnects, advanced 2D/2.5D/3D packaging, and key metrics including energy per bit, bandwidth density, data rate, and bit-error rate (BER) are introduced. We also examine how package technology affects the optimum electrical interface.

Package-channel behaviour is then covered, including insertion loss, reflections, inter-symbol interference (ISI), crosstalk, termination, and signal integrity. Single-ended, differential, ground-referenced, and simultaneous bi-directional signalling are compared in terms of pin efficiency, noise immunity, power, and circuit complexity.

TX and RX topics include voltage- and current-mode drivers, output impedance, termination, signal swing, TX equalization, amplification, sampling, offset, sensitivity, and continuous-time linear equalization (CTLE). The focus is on translating link specifications into circuit requirements and understanding how circuit choices interact with package-channel characteristics.

A dedicated session covers forwarded-clock link design, including multiphase clock generation, phase interpolators, clock distribution, lane-to-lane skew and de-skew, and timing calibration. The course examines source-synchronous timing and how timing budgets influence circuit and system design.

The final lecture focuses on HBM links, where extremely high aggregate bandwidth must be delivered under tight power, area, timing, and packaging constraints. Topics include HBM architecture, signalling, data and clock paths, timing relationships, channel characteristics, and circuit-design challenges as memory bandwidth and per-pin data rates increase.

Two real-world design projects emphasize practical design methodology and provide hands-on experience from specifications through circuit implementation and simulation. The first covers CTLE design from channel-loss specifications through transfer-function requirements, circuit design, transistor sizing, and simulation. The second focuses on TX and package-channel co-design, using link requirements to guide circuit-level decisions and evaluate performance.

Each lecture is accompanied by a homework assignment that reinforces key concepts through practical analysis and design. Assignments may involve hand calculations, circuit design, simulation, or MATLAB-based modelling, covering topics such as package-channel analysis, signalling comparisons, transmitter sizing, CTLE design, and forwarded-clock de-skew.

The course is intended for analog and mixed-signal IC, SerDes, I/O, and memory-interface designers, as well as engineers, graduate students, and researchers working on chiplets, advanced packaging, processors, accelerators, and HBM systems. Participants should have basic analog CMOS circuit-design and transistor-level simulation experience; familiarity with high-speed circuits, transmission lines, or SerDes is useful but not essential.